(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to methods used to fabricate metal oxide semiconductor field effect, (MOSFET), devices, with improved performance, and increased device density, via use of MOSFET process innovations.
(2) Description of Prior Art
Major objectives of the semiconductor industry continues to be increased device performance, and decreased process costs. The trend to micro-miniaturization, or the use of sub-micron features, have allowed these objectives to be successfully addressed. The creation of MOSFET devices, with sub-micron features, results in a reduction in performance degrading parasitic capacitances, while the use of sub-micron features allow the attainment of smaller semiconductor chips, however still accommodating the level of integration supplied by larger counterparts, thus enabling a greater number of smaller semiconductor chips to be obtained from a specific size starting wafer, thus reducing the processing cost for a specific semiconductor chip.
In addition to micro-miniaturization, basically obtained via advances in the photolithographic discipline in terms of more advanced exposure cameras, and more sensitive photoresist materials, specific MOSFET process sequences have also allowed specific MOSFET features to be reduced in size, and by so doing improve device performance. This invention will describe novel MOSFET process sequences used minimize specific MOSFET features, thus enhancing device performance. The formation of a source/drain extension, or a lightly doped source/drain, (LDD), region, accomplished after formation of other features, such as heavily doped source/drain regions, or polycide gate structures, allow this LDD region to maintain the minimum designed dimensions, as a result of avoiding the high temperature processes used for formation of heavily doped source/drain regions, or polycide gate structures. In addition these novel process sequences, used to create the source/drain extension, also allows the attainment of shallower, heavily doped source/drain regions, resulting from the diffusion from an overlying doped epitaxial layer, as well as resulting in a planar top surface topography, both contributing to increased device performance, and increased device density, or process cost reduction. Prior art, such as Hong, in U.S. Pat. No. 5,899,719, describes a sub-micron MOSFET device, featuring a source/drain extension. However that prior art does not feature the use of selectively grown epitaxial silicon to define a subsequent gate region, and to supply the dopants needed for the heavily doped source/drain region.